Summary

The AP-101S computer architecture was built by integrating three distinct systems. First, the CPU core was redesigned to be pipelined, meaning instructions were processed in six sequential steps rather than just a single block. This new structure handled instruction address translation, fetched the code, decoded it, and then calculated the operand's memory address. The pipelining capability allowed the system to handle multiple instruction cycles simultaneously, significantly improving throughput compared to older single-stitch designs. Second, the original Shuttle computer's IO processor was retained to manage input/output operations for the new CPU. Third, the computer relied on semiconductor memory derived from the AP-102 architecture, which served as the primary storage device for executing these high-speed instructions.

Title

Ken Shirriff's blog

Description

Ken Shirriff's blog

Keywords

computer, memory, computers, shuttle, space, core, instruction, system, processor, instructions, pages, model, unit, performance, storage, second, bits

NS Lookup

A 172.67.133.98, A 104.21.5.119

Dates

Created 2026-03-09

Updated 2026-04-15

Summarized 2026-04-16